AES IP Core

Features

• High performance AES IP Core (Encryption and Decryption)
• Supports different key lengths of 128, 192, and 256 bits
• The core supports any input pattern with fixed length of 128 bits
• Pipelined core available

 Functional Description

Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 192 and 256).

The AES IP Core is fully verified against 'The advanced encryption standard algorithm validation suite (AESAVS)'.

The implementation of the AES IP Core exhibits very low latency, high speed, and low gate count with a simple interface for easy integration within SoC applications.

IP Deliverables 

• Synthesizable Verilog
• System Model (Matlab) and documentation
• Verilog Test Benches
• Documentation

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