AHB Slave
Features
- AHB Slave
- Configurable and customizable
- Synthesized on ASIC 40nm TSMC and Xilinx FPGA
- Compatible with AMBA standard
Functional Description
AHB:
The Advanced High-performance Bus (AHB) is used for connecting components that need higher bandwidth on a shared bus.
These could be a internal memory or an external memory interface, DMA, DSP etc but the shared bus would limit the number of agents.
This is a shared bus protocol for multiple masters and slaves, but higher bandwidth is possible through burst data transfers.
The latest spec can be found on ARM website and is relatively easy to learn.
AHB-lite
protocol is a simplified version of AHB.
The simplification comes with support for only a single master design and that removes need for any arbitration, retry, split transactions etc.
Applications
- SOC Designs
- High Performance Bus
- AHB Masters
IP Deliverables
- Synthesizable Verilog
- System model (Matlab)
- Verilog test bench
- Comprehensive documentation
Download