This three day course provides attendees with a solid and intuitive understanding of the problems encountered in the digital implementation of communications functions related to 4G LTE Technology.

The focus is on real algorithms that are commonly employed in typical communications transceivers.

These include the channel estimation and equalization, synchronization, frequency offset estimation and correction, and the digital chain, as well as the digital front end.

Commonly overlooked aspects, such as the effects of noise and rounding, and quantization are also examined in detail. Furthermore, we closely examine the design methodology for digital circuitry targeting an LTE receiver.

This three day course provides attendees with a solid and intuitive understanding of the problems encountered in the digital implementation of communications functions related to DVB-C Technology.

The focus is on real algorithms that are commonly employed in a DVB-C communications transceivers.

These include the adaptive equalizer, and the digital chain, as well as the digital front end. Commonly overlooked aspects, such as the effects of noise and rounding, and quantization are also examined in detail. Furthermore, we closely examine the design methodology for digital circuitry targeting a DVB-C receiver.

Module 0: Introduction

  • Architecture and System Analysis
  • SDR Approach
  • Development Stages

Module 1: Digital Communications Fundamentals

  • Communications System Block Diagram
  • Link Budget Analysis
  • Bandlimited Communications
  • Design of various blocks
  • Hard demapper and soft LLR demapper
  • Matched Filter
  • Putting it altogether
  • Matlab Exercises

The attendees will have developed a  Matlab (Octave) design of a perfectly synched communications system at the end of Module 1

Module 2: Channel Estimation and Equalization

  • Single path channel with a phase
  • Channel Models
  • Effect of a multi-tap channel and Intersymbol Intereference
  • Channel Estimation Via Training
  • Equalization: Zero Forcing, MMSE, Decision Feedback
  • Fractional Spaced equalization
  • Adaptive Equalization
  • Matlab Exercises

The attendees will have developed a Matlab (Octave) design of channel estimation and equalization algorithms that can be used with a multi-tap or a multi-path channel

Module 3: Timing Acquisition and Tracking

  • Autocorrelation properties of training sequences
  • Channel and frame timing estimation via correlation of training sequences
  • Matched filter timing for a single path channel
  • Symbol Timing tracking
  • Adaptive equalizers as a possible time tracking algorithm
  • Matlab Exercises

The attendees will have developed a Matlab (Octave) design of time acquisition and tracking algorithms including early-late loop for example

Module 4: Frequency and Phase Acquisition

  • Possible sync sequences design for initial phase and frequency estimation
  • Frequency and phase tracking via a second order loop
  • Phase tracking within an adaptive equalizer
  • Matlab Exercises

The attendees will have developed a Matlab (Octave) design of frequency and phased tracking algorithms including a second order PLL

Module 5: Error Correction Coding

  • Block Coding and decoding: Binary BCH and nonbinary RS codes
  • Convolutional Codes and the Viterbi Algorithm
  • Trellis Coded Modulation
  • Turbo Codes and iterative decoding
  • LDPC codes and iterative decoding
  • Matlab Exercises

The attendees will have developed a Matlab (Octave) design that uses available libraries and encode and decode various error correction codes

Other Modules include: OFDM systems, MIMO systems, Fixed Point Implementation for bit true RTL, AGC and IQ imbalance corrections.

Other required modules can be custom prepared

The “Long Term Evolution,” LTE, is the up and coming technology for 4G wireless connectivity and beyond. In this course, the basic tenets and structure for the LTE will be covered, paying special attention to the physical and MAC layer operation. The course is an ideal starting point for technical designers who will embark on designing and implementing LTE system. The course also offers focused and selected overview for managers and leaders to gain insight of the technology and its challenges.

Course topics include:

  1. Evolution of the communication systems to LTE.
  2. LTE General Architecture and channels.
  3. MAC layer Procedures: Resource Allocation.
  4. Downlink channels operations.
  5. Uplink channels operations.
  6. Physical layer procedures & Scheduling.
  7. RLC, Data Flow, Radio Resource Management and Mobility Management.
  8. LTE-A: Carrier Aggregation, CoMP, Relaying, MIMO structure and Het-Nets.
  9. Supporting IoT in LTE-A: Narrow-band LTE.
  10. Roadmap to 5G.

What you will learn:
Participants in the course are expected to gain the knowledge of:

  • LTE as a new trend and how it compares to older 3G standards and the competitor WiMAX standard.
  • The structure of the physical layer of the different LTE sections both uplink and downlink.
  • Physical layer procedures, MAC layer Procedures, RLC, Data flow, Resource and Mobility management.
  • Fundamentals of LTE-A: Changes to the LTE standard to support LTE-A features.
  • Future trends in LTE-A: Narrow-band LTE.

Who Should Attend:

Engineers and Technical Managers and other personnel involved in product marketing, production, test and development of components, circuits and systems for LTE and/or wireless systems in general. It is also applicable for those deploying and maintaining such systems in the field.

Prerequisite:

Basic technical background in electrical, electronics, physics, mathematics at Diploma or

Degree levels, with good understanding of digital communication system.

Course Methodology:

This course is presented classroom style, with short lab exercises to re-enforce the concepts taught.

Course Duration: 4 days, 9am ~ 5pm

Course Structure:
Day 1 – LTE OVERVIEW and uplink transmitter details:

  •  LTE history and evolution.
  • LTE uplink and downlink general overview.
  • Comparison between LTE and 3G standards.
  • Comparison between LTE and WiMAX.
  • The downlink/ uplink structure of the LTE.

     o Different logical channels and their block diagrams.
     o Different physical layer channels and their basic blocks.
     o TDD/FDD operation.
     o Downlink and Uplink Frame structures in the LTE.
     o Wireless Communication fundamentals: Fading and channel estimation.

Day 2 – LTE enabling technologies:

– General Overview of main enabling technologies in LTE:

 Multicarriermodulation.
 OFDM frame structure and cyclic prefix. 

 OFDM in LTE.

o MIMO :
 Diversitytechniques.

 MIMO multiplexing techniques. 

o MIMO in LTE-A.

o Physical layer procedures. 

Day 3–LTE-MAC layer procedures:

o MAC layers fundamentals: Resource Allocation techniques. 

o LTE MAC layer overview.

o Downlink operation.

o Uplink operation.          

o RLC.

o Data Flow, Radio Resource Management, Mobility Management.    

o Carrier Aggregation.

o Coordinated Multipoint.

Day 4 –Advanced Topics in LTE:

o Relaying.

o Interference mitigation.

o Heterogeneous networks.

o Implementation and Testing issues of LTE/ LTE-A. 

o Narrow Band LTE:

      o Overview of IoT.

      o What is new in oLTE-Rel 13. 

  o Roadmap to 5G.

   

Overview:

This three day course provides attendees with a solid and intuitive understanding of the problems encountered in the digital implementation of communications SoC functions. The focus is on real algorithms that are commonly employed in communications transceivers. These include FFTs, digital filters, digital mixers, and CORDIC blocks. Those hardware accelerators work in conjunction with a programmable core. Commonly overlooked aspects, such as the effects of noise and rounding, and quantization are also examined in detail. Furthermore, we closely examine the design methodology for digital circuitry targeting SoC applications with a case study of an actual communications SoC (Digital Video Broadcasting receiver).

What you will learn:

  • Introduction and Design Methodology

  • Functional Design Partitioning

◦ Hardware/software partitioning

  • Fixed-point Algorithm Development

    • Scaling and Round-off Noise

    • Quantization Effects in Digital Filters

  • Digital Arithmetic Circuit Implementations

  • Scheduling and Allocation Techniques

  • Verification

  • Interfacing to programmable processor

  • Busses and register maps

  • Major Digital Blocks (reusable IP)

    • CORDIC Implementations

    • IIR Filter Implementations

    • FIR Filter Implementations

    • Fourier Transform Implementations

    • Error Correction Blocks

    • Digital Mixers

  • Finite State Machines

    All of the above is to be considered essentially from a circuit point of view. An actual/exemplary Verilog HDL design implementation of a DVB-C receiver is included to highlight circuit parameters, including timing, area and power consumption, etc. Xilinx ISE/Modelsim is used for demonstration purposes.

Who Should Attend

Engineers and Technical leads and engineering managers who are involved in product marketing, production, test and development of digital signal processing ASICs and embedded systems and/or their application.

Prerequisites

Technical background in electronics, communications at Degree levels.

Course Methodology

This course is presented classroom style, with lab exercises and demos to illustrate the concepts taught.

Course Structure

  • Introduction and Design Methodology

    • Z-Transform review

    • From Spec to Architecture

  • Digital Arithmetic Circuit Implementations

    • Adders

    • Round / Saturate blocks

    • Multipliers

    • Complex Multipliers

  • Scheduling and Allocation Techniques

    • Pure ASIC versus embedded processor

    • Overall state machine

  • Scaling and Round-off Noise

    • Limit cycles

    • Quantization noise analysis

    • Architecture impact of quantization noise

  • Digital Mixers

    • 2 multiplier mixer

    • 4 multiplier cross mixer

  • CORDIC Implementations

    • Arctan

    • Vector rotation

    • Sine/Cosine

  • Filter Implementations

    • IIR Filter Implementations

    • Conventional FIR structure

    •  Practical FIR structures

    • Fixed coefficient FIR filters

  • Fourier Transform Implementations

  • Finite State Machines

    • Mealy FSM implementations

    • Moore FSM implementations

    • Pseudo Moore FSM with registered outputs

Overview:

You will gain a solid and intuitive understanding of the problems encountered in the digital implementation of communications SoC functions. The focus is on real algorithms that are commonly employed in communications transceivers. The course will start from basic Verilog building blocks all the way to building a real communications systems

Some of the Covered Material:

A. Verilog

1-Introduction to Verilog HDL

2-Data Types

3-Module Construction

4-Operators

5-Continuous Assignment with logic operators

6-Continuous Assignment with conditional operators

7-Procedural Blocks

8-Procedural Statements

   i.if/else

  ii.case/casex/casez

  iii.loops

  iv.System Tasks

9-Describing Combinational Logic.

  i.Encoders

  ii.Decoders

  iii.Multiplexers

  iv.De-multiplexers

10-Describing Sequential Logic

  i.Registers and registered logic

  ii. Counters

  iii. Memories

11-Test Benches

  i.Simple test benches

  ii.Self checking test benches

12-Finite State Machines

  i.Moore Machines 

 ii.Mealy Machines

 iii.Examples

B. FPGA Technology

 1-Introduction

 2-Xilinx FPGAs (Series 7)

   i.Configurable Logic Block

   ii.Select I/O

   iii.Memory Resources

   iv.DSP Block

   v.Clocking Resources

 3-Xilinx Vivado

   i. Synthesis

   ii. Implementation


 4-Static Timing Analysis 

5-Design Constraints

   i.Basic Constraints

   *Primary Clock Constraints
   *Virtual Clock Constraints
   *Derived/Generated Clock Constraints
   *Input/Output Constraints

  ii.Advanced Constraints

    • False Paths
    • Max Delay / Min Delay
    • Multicycle Paths
    • Case Analysis
    • Disable Timing