DDR3 Controller

Features

• Provides 128-bit AXI interface for data
• Provides 32-bit APB interface for configuration
• Supports all the JEDEC standards up to 800MHz of DRAM frequency
• Supports 72 bit wide DRAM interface (64 bit for data and 8bits for ECC)
• Supports up to 4 ranks of UDIMM, RDIMM and component interfaces

Functional Description

DDR3 controller IP serves read or write data request from AXI master to be performed on DDR3 memory. JEDEC standard JESD79-3F specifies interface to DDR3.

The specification puts requirement on the controller to maintain order of command and meet the timing between them for successful data transactions. Controller interfaces to DRAM via Synopsys PHY.

Interface between controller and PHY is defined by DFI v2.0. Different DRAM configurations have different timing requirements.

These are configured in DRAM controller via APB interface in the register space.

Applications
SoC design for:

• Ultra mobile Computers
• Tablet Computers
• Smart Phones

IP Deliverables

• Synthesizable Verilog RTL
• Test bench/Test plan
• IP Integration guidelines/Documentation

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