DVB-T2 Rx Bit Chain
Features
- Short and Long Frames
- SISO
- Flexible channel BW (1.7, 5, 6, 7, 8, and 10) MHz
- Flexible modulation (QPSK, 16QAM, 64QAM, and 256QAM)
- Flexible FFT size (1, 2, 4, 8, 16, and 32) K
- Flexible guard interval (1/128, 1/32, 1/16, 19/256, 1/8, 19/128, and 1/4)
- Flexible coding rate (1/2, 3/5, 2/3, 3/4, 4/5, and 5/6)
- Soft demodulation
- Layered Min-Sum LDPC decoder
- BCH decoder
Functional Description
In the DVB-T2 transmission, the Physical Layer Pipes (PLPs) carries the MPEG-2 Transport Streams (TSs). The system input/inputs may be one or more MPEG-2 TS/TSs. The system output is typically a single signal to be transmitted on a single RF channel. The maximum input rate for any TS, including null packets, shall be 72 Mbit/s. The maximum achievable throughput rate, after deletion of null packets when applicable is more than 50 Mbit/s (in an 8 MHz channel). The generation of data PLP signal consists of the following processes:
- Randomizer
- BCH Encoder
- LDPC Encoder
- Bit Interleaver
- Bit2Cell De-Mux
- Constellation Mapper
- Constellation Rotation and QDelay Generation
- Cell Interleaver
- Time Interleaver
- Frequency Interleaver
This design of the DVB-T2 Rx Bit-Chain is used for DVB-T2 PHY to be supplied as a portable and synthesizable Verilog IP. The system was designed to be used in conjunction with RF tuner and DVB-T2 Signal-Chain.
The data bit chain demodulates the incoming data stream using either 2D log-likelihood ratio (LLR) de-mapping, or 1D LLR, depending on whether the constellation rotation is done in the transmitter, or not. The low density parity check (LDPC) block and the BCH decoder deal with short frame and normal frame types. The LDPC decoder decodes iteratively using layered Min-sum algorithm. The BCH decoder can correct up to 12 bits, or 10 bits per codeword, depending on the frame type and coding rate.
IP Deliverables
- Synthesizable Verilog
- System Model (Matlab)
- Verilog Test Benches
- Documentation
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