HomePlug Turbo Decoder

Features

• Supports rates½ and 16/18 coded input.
• FEC block size support : 16, 72, 136, 264, 520 bytes
• Configurable number of Iterations
• LLR width 14 bits
• Max-Log Map algorithm.VK-3052
• Compliant with HomePlug AV Specification Version 2.1
• Cyclic Redundancy check (CRC)
• Channel Interleaving / DeInterleaving
• Bypassing mode for Scrambler/De-Scrambler
• Bypassing mode for Channel Interleaver/DeInterleaver
• Puncture/De-Puncture units
• Turbo Encoder design

Functional Description

On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) HomePlug 1.0.1 Frame Control (FC) data, B) HomePlug AV2 Frame Control data, and C) HomePlug AV2 Payload data. This IP implements the HomePlug AV2 payload data stream.The design includes a CRC, a Scrambler, a Turbo Convolutional Encoder, and an Interleaver.

On the receiver side, The AV2 Payload Data Decoder consists of a Channel De-interleaver followed by a Turbo Convolutional Decoder, a De-scrambler and a CRC removalunit to recover the AV2 Payload data.

IP Deliverables

• Synthesizable Verilog
• System Model (Matlab) and documentation
• Verilog Test Benches
• Documentation

Download