ISDB-S3-LDPC-BCH Decoder

Features

• Layered Decoding
• Minimum sum algorithm
• Soft decision decoding
• BCH decoder works on GF (2^16 ) and corrects up to t =12 errors
• ARIB STD-B44 2.0 standard compliant
• The code length Nldpc is 44880 bits for all the supported code rates

Benefits

• Low-power and low-complexity design
• LDPC decoder, Energy dispersal and BCH decoder
• Frame-to-frame on-the-fly configuration
• Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance

IP Deliverables

• Synthesizable Verilog
• System Model (Matlab) and documentation
• Verilog Test Benches
• Documentation

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