L3 Cache Controller

Features

• Supports cache size of 8 MB (4 sets/2MB each set)
• Fixed line, length of 64 bytes.
• 16-way set associativity of register
• Data RAM is byte writable
• 1,2,4,8,16-way SRAM mode support
• Single-error correction and double-error detection for tag and data
• Tag and data ram repair logic
• Interrupt from L3 cache
• Cache maintenance operation

Functional Description

Level-3 (L3) cache controller has L3 cache and looks for tag ram to see if data
is available in the cache. If data is available in the cache it provides data
to cache coherence interconnect (CCI). In case of write, it will update the tag
and data. It also supports other cache operations like clean, invalidate and
eviction of cache.

Applications
SoC design for:

• Ultra mobile Computers
• Tablet Computers
• Smart Phones

IP Deliverables

• Synthesizable Verilog RTL
• Test plan (formally verified using Jasper tool)
• IP Integration guidelines/Documentation

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