LTE Lite

Features

• User Equipment (UE) LTE Lite, compliant to CAT 0/1 PHY
• Supports IF input
• Flexible channel BW (1.4, 3, 5, 10, 15, 20) MHz
• Modulation (QPSK, 16QAM, 64QAM)
• Time tracking
• Measurements
• Parallel and Serial outputs

Functional Description

The LTE Lite PHY supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the demodulator is automated by a master finite state machine.

The design interfaces to an external Analog to Digital converter, which receives the analog signal from the external RF tuner. The included frequency correction can compensate for 500KHz frequency offsets for up to 20MHz channel bandwidth. The timing correction can correct mismatches as large as 50ppm.

IP Deliverables

• Synthesizable Verilog
• System Model (Matlab) and documentation
• Verilog Test Benches
• Documentation

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