LTE Rx Bit Chain
Features
- LTE: CAT 0, 1, 2, and 3 PHY
- Flexible channel BW (1.4, 3, 5, 10, 15, and 20) MHz
- Flexible modulation (QPSK, 16QAM, 64QAM)
- Downlink resource block allocation (Type 0, Type 1, and Type 2 localized)
- Soft demodulation
- Parallel Turbo decoding
- HARQ retransmission combining
- Compensation of AGC scaling at each receiver antenna
Functional Description
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block). The modulation format of PDSCH channel may be QPSK, 16 QAM or 64 QAM. The data (Transport block) arrives to the PDSCH coding unit every transmission time interval (TTI). The generation of the PDSCH signal consists of the following processes:
- CRC attaching to the transport block
- Segmentation
- CRC attaching to the segments
- Channel coding
- Rate matching
- Scrambling
- Modulation
- Mapping to resource elements
This design of the LTE Rx Bit-Chain is used for CAT 0, 1, 2, and 3 LTE PHY to be supplied as a portable and synthesizable Verilog IP. The system was designed to be used in conjunction with RF tuner and LTE Signal-Chain.
Firstly the Resource Element De-mapper demapps the complex modulated symbols and the complex channel estimates which are mapped to the resource elements.
The AGC Scaling Compensation block multiplies these complex modulated symbols and the complex channel estimates by their AGC scales for each receiver antenna.
The Channel Equalizer equalizes the effect of the channel where it just a multiplication by the conjugate of the channel estimate in the case of 1×1 antenna configuration.
In the case of 1×2 antenna configuration, the Channel Equalizer applies maximum ratio combine (MRC).
In the case of 2×2 or 4×2 antenna configurations, the Channel Equalizer applies zero forcing equalizer (ZF) or K-best MIMO decoder which is a special case from the sphere decoder.
QAM De-mapper consists of QPSK, 16-QAM and 64-QAM demodulation techniques, and the output from the De-mapper block is a soft output LLR 'Log Likelihood Ratio'.
The De-scrambler accepts the LLR soft bits and output the descrambled soft bits according to the scrambling sequence.
The Turbo Rate De-Matching will do the reverse operation of Turbo Rate Matching in downlink receiver which will operate on a specified number of soft LLRs from descrambler.
Parallel Turbo Decoder algorithm is used in which the incoming block is decomposed to sub-blocks to facilitate the sliding windows processing technique.
That technique allows independent decoding of sub-blocks without degradation in error-correction performance.
Finally the Cyclic Redundancy Check (CRC) which is the most common technique of the redundancy checking techniques is done.
IP Deliverables
- Synthesizable Verilog
- System Model (Matlab)
- Verilog Test Benches
- Documentation
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